The present invention generally relates to semiconductor device manufacturing methods and more particularly to a wafer level bumpless method of making a flip chip mounted semiconductor device.
Conventional flip chip mounting methods connect a bumped semiconductor die to a land pattern on a substrate. The bumps, which may be formed of solder and gold, are first formed on conductive pads of the semiconductor die. Thereafter, heat and pressure may be applied to the bumps to form the connection paths between the semiconductor die and the substrate. When needed, a flowable material may be introduced into a recess formed between the semiconductor die and the substrate to improve the mechanical connection between the semiconductor die and the substrate.
Conventional flip chip technology has been employed to fabricate low pin count semiconductor devices mounted to lead frames. As disclosed in U.S. Pat. No. 5,817,540, the method generally includes flipping a die onto a lead frame with the use of bumps as interconnects. The wafer may be bumped and sawed beforehand. Upon separating the dies, the bumped dies may be flipped directly onto matching lead frames. Connection between the die and the lead frame is achieved through re-flowing of the solder. When solder bumps are not used as an interconnection, conductive paste or conductive-filled epoxy may be used. After the die is connected to the lead frame, a dielectric layer, or an under-fill material, may be dispensed to cover the gap between the die and the lead frame to prevent shorting and to provide adhesion between the die and lead frame.
Conventional flip chip technology suffers the disadvantage of requiring the costly bumping of the semiconductor die. Furthermore, in the case where the semiconductor die contact pads are formed of aluminum, an under-bump metallization (UBM) layer must be employed to facilitate the user of solder or other bonding materials. Deposition of the UBM layer adds additional cost to the semiconductor package.
There is therefore a need in the art for a wafer level bumpless method of making a flip chip mounted semiconductor device package which overcomes the disadvantages of the prior art. Preferably the wafer level bumpless method reduces the cost of fabricating the flip chip mounted semiconductor device while providing improved reliability of board level packaging. Furthermore, the wafer level bumpless method preferably provides for reductions in the thermal expansion mismatch between the lead frame and a printed circuit board and a larger connection area for board level mounting.